This invention relates to thin film transistors, thin film transistor arrays, and a method of preparing the same.
It has been heretofore proposed to utilize thin film transistors and particularly an array of thin film transistors to control and drive display panels such as, for example, liquid crystal displays, electroluminescent mediums and the like. Thin film transistors in this application offer an attractive substitute to the utilization of silicon technology because of the size limitation problems associated with that technology. A large number of thin film transistors can be prepared within any given size area and in a density satisfactory for pictorial presentation. Examples of thin film transistors and associated display panels are set forth in U.S. Pat. Nos. 4,040,073 and 4,042,854.
Fabrication of thin film transistor arrays requires the generation of well defined geometric patterns of metals, semiconductors and insulators. These are deposited in layers to form the transistor structures and circuit interconnections. Patterns can be generated by shadow masking or photolithographic methods. The first, a popular classic method, relies on a series of mechanical masks to define pattern geometries whle shielding the remainder of the substrate from the deposition source. The photolithographic method is attractive for cost effective fabrication of large area circuits containing a high density of components.
There are two photolithographic fabrication processes, the subtractive and the additive. In the subtractive process, patterned photoresist layers mask desired areas of deposited materials while unwanted regions are removed by any suitable means, such as, chemical etching, plasma etching, ion milling or the like. In the additive process, unwanted regions are masked by photoresist layers prior to the deposition of the material. Immersion of the substrate in a suitable solvent for the photoresist layer dissolves the photoresist material thereby lifting away the unwanted material and leaving on the substrate a well defined circuit pattern. Alternatively, by means of a stripping, such as, plasma stripping, may be used to remove both the photoresist and unwanted material.
Two critical technological tasks encountered in the fabrication of multi-layered thin film transistor arrays are the formation of electrical contact between circuit elements located at different levels and the electrical isolation of conductors crossing over patterns of metals and semiconductor. In one configuration of thin film transistors, semiconductor films extend from the substrate level to source-drain pads at the next level. The gate oxide and electrode must follow this contour. Gate structures and crossovers form the third and fourth layers. Topography of the completed device is that of multilayered mesas with varied geometries and individual heights which range from about 100 Angstroms to several thousand Angstroms. Coverage of mesa steps with continuous films of uniform thickness poses difficulties due to the sharply defined vertical edges of patterns delineated by processing steps such as the photolithographic fabrication process briefly described above. Because of the sharp edges, the subsequently deposited layers as they form over the sharp edges are thinner than on the planar surface of the patterns previously prepared. This thinning causes open or shorted devices to occur. It can be readily seen that, in a display device where pictorial presentation is desired, substantially all of the thin film transistors must be operative in order to prevent imperfections in the completed display device.
Accordingly, it is a primary object of this invention to provide a planar thin film transistor.
It is another object of this invention to provide a thin film transistor array wherein the plurality of thin film transistors forming a part of the array are planar in nature.
It is still another object of this invention to provide a method of making planar thin film transistors.
______________________________________ Page et al U.S. Pat. No. 3,669,661 June 13, 1972 Havas et al U.S. Pat. No. 4,035,276 July 12, 1977 Luo U.S. Pat. No. 4,040,073 Aug. 2, 1977 Luo et al U.S. Pat. No. 3,042,854 Aug. 16, 1977 Takemoto U.S. Pat. No. 4,055,885 Nov. 1, 1977 Havas et al U.S. Pat. No. 4,090,006 May 16, 1978 IEEE TRANSACTIONS OF ELECTRON DEVICES, Vol. ED-20, No. 11, November 1973, "A 6 .times. 6 Inch 20 Lines- per-Inch Liquid-Crystal Display Panel", T. P. Brody, Juris A. Asars, and Douglas Dixon. ______________________________________
A brief description of the publications cited above follows immediately below.
Page et al. discloses a method of producing a thin film transistor on a substrate by evaporating layers of various materials from sources positioned at various angles to the substrate normal.
Havas et al. ('276 and '006) relates to a method of forming coplanar thin films on a substrate by forming a pattern of a first thin film and an expendable material. Depositing a second thin film by RF sputtering at a bias and etching away the expendable material.
Luo discloses a double gated thin film field effect transistor wherein cadmium selenide is the semiconducting material, indium is provided on either side of the conducting channel to enhance transconductance and the source and drain contacts are a combination of an indium layer and a copper layer.
Luo et al. discloses a large area flat panel solid-state display in which thin film transistor addressing and control circuitry are integrally connected to the display medium.
Takemoto discloses a method of making a charge coupled semiconductor device whereby oxide regions are formed on sides of a first series of electrodes which face each other and positioning a second series of electrodes between the oxide regions.
The IEEE article describes an integrated 14,000 picture element 36-in.sup.2 flat screen display panel constructed by a combination of thin-film transistor-nematic liquid-crystal technology.